Alternatively, the first memory 30 and/or the second memory 32 can be internal to the network processor 18. 2, the first memory 30 and the second memory 32 reside externally to the network processor 18. The second memory 32 can be coupled to the queue manager 27 and other components of the network processor 18. The first memory 30 has a memory space for storing data. The memory controller 34 initiates queue commands in the order in which they are received and exchanges data with the queue manager 27. The network processor 18 includes a memory controller 34 that is coupled to a first 30 and second memory 32, and a third memory 17 containing software instructions for causing the engines to operate as discussed in detail below. For example, the queue manager 27 includes the CAM 29.

Each programming engine contains a multiple-entry content addressable memory (CAM) to track N of the most recently used queue descriptors where N represents the number of entries contained in the CAM. 2, the network processor 18 has multiple programming engines that function as a receive pipeline 21, a transmit scheduler 24, a queue manager 27 and a transmit pipeline 28. H04L49/9089- Reactions to storage capacity overflow replacing packets in a storage arrangement, e.g.H04L49/9084- Reactions to storage capacity overflow.H04L49/901- Buffering arrangements using storage descriptor, e.g.H04L- TRANSMISSION OF DIGITAL INFORMATION, e.g.241001522296 Erithacus rubecula Species 0.000 description 2.OC()=O UIIMBOGNXHQVGW-UHFFFAOYSA-M 0.000 claims description 196

UIIMBOGNXHQVGW-UHFFFAOYSA-M buffer Substances.Assignors: ADILETTA, MATTHEW J., BERNSTEIN, DEBRA, ROSENBLUTH, MARK B., WOLRICH, GILBERT Publication of US20030115347A1 publication Critical patent/US20030115347A1/en Application granted granted Critical Publication of US7269179B2 publication Critical patent/US7269179B2/en Status Expired - Fee Related legal-status Critical Current Adjusted expiration legal-status Critical Links Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.) Filing date Publication date Application filed by Intel Corp filed Critical Intel Corp Priority to US10/024,657 priority Critical patent/US7269179B2/en Assigned to INTEL CORPORATION reassignment INTEL CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Original Assignee Intel Corp Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.) Adiletta Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.) Expired - Fee Related, expires Application number US10/024,657 Other versions US20030115347A1 Google Patents Control mechanisms for enqueue and dequeue operations in a pipelined network processorĭownload PDF Info Publication number US7269179B2 US7269179B2 US10/024,657 US2465701A US7269179B2 US 7269179 B2 US7269179 B2 US 7269179B2 US 2465701 A US2465701 A US 2465701A US 7269179 B2 US7269179 B2 US 7269179B2 Authority US United States Prior art keywords queue memory data store requests Prior art date Legal status (The legal status is an assumption and is not a legal conclusion. Google Patents US7269179B2 - Control mechanisms for enqueue and dequeue operations in a pipelined network processor

US7269179B2 - Control mechanisms for enqueue and dequeue operations in a pipelined network processor

Enqueue dequeue